Bluespec Targets Low-Power ESL Synthesis; Added Clock Management, Power Management and Formal Clock Verification Capabilities Accelerate SoC Design
WALTHAM, Mass.—(BUSINESS WIRE)—June 13, 2005—
Bluespec Inc., www.bluespec.com, developer of the only
ESL synthesis solution for control logic and complex datapaths in chip
design, announced today it has added low-power ESL synthesis with
integrated clock and power management and formal clock verification
capabilities to its ESL synthesis EDA toolset. Bluespec provides ASIC
and FPGA engineers with the unique capability to validate proper
multiple clock domain implementations during the synthesis process
rather than delaying the discovery of synchronization issues in
working silicon when they are hard and expensive to correct. Bluespec
will be showcasing these capabilities at DAC 2005 in Anaheim, Calif.
June 13-17, 2005 at booth #432.
As SoCs continue to become larger and faster, gated clocks and
multiple clock domains are increasingly used to manage power, to
support multiple, varied communication interfaces, and to re-use older
IP, that can demand different clock requirements. Interconnection
among these different clock domains has become difficult to manage and
prone to error, as most commercially available verification tools do
not guarantee correct implementation to handle metastability. As a
result, synchronization issues are sometimes not discovered until the
chip is manufactured into silicon - adding significant delays and
costs to the design of the chip. In addition, implementing and
managing control logic around clock gating for power management is
burdensome and contributes to design errors.
Bluespec has added integrated clock management and formal clock
connectivity verification to enhance its multiple clock domain (MCD)
support. Bluespec's toolset automates gated-clock implementations for
power management by automatically identifying and managing interface
communications between active and inactive clock domains. By
incorporating clocking into its semantic model, Bluespec's toolset
simplifies complex clock topology implementations and ensures that
mis-connections are caught at the time of synthesis.
"We are one of the few companies addressing the increasing
challenges presented by MCDs - and have taken the lead in the
high-level synthesis space by delivering the first tool with
integrated clock management and verification to minimize their costs,"
said Sathyam Pattanam, vice president of engineering at Bluespec.
"Bluespec is tightly integrated with existing tools and methodologies,
and, more importantly, with the complex design needs of engineers, who
cannot afford to compromise in results as well as capabilities."
As a demonstration vehicle for this capability, Bluespec is
showing at DAC an industry standard physical layer device (PHY) design
featuring serial bit stream clock and data recovery implemented with
multiple clock domains. "PHYs are tough to design. Frankly, most
people are incredulous that ESL synthesis can handle a PHY," said
George Harper, vice president of marketing at Bluespec. "To them we
say, you'll be even more impressed when you see the speeds, the levels
of logic and the tightness of the design."
About Bluespec
Bluespec Inc. manufactures an industry standards-based Electronic
Design Automation (EDA) toolset that significantly raises the level of
abstraction for hardware design while retaining the ability to
automatically synthesize high quality RTL, without compromising speed,
power or area. The toolset, the only one focused on control and
complex datapaths, allows ASIC and FPGA designers to significantly
reduce design time, bugs and re-spins that contribute to product
delays and escalating costs. More information can be found on
www.bluespec.com or by calling 781-250-2200.
Copyright 2005 Bluespec, Inc. Bluespec is a trademark of Bluespec,
Inc. All other brands, products, or service names may be trademarks or
service marks of the companies with which they are associated.
Contact:
Bluespec, Inc.
George Harper, 781-250-2200
Email Contact
or
SHIFT Communications
Lynne Cavanaugh, 617-681-1233
Email Contact
